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| march 2015 doc id 18441 rev 4 1/72 72 AN3338 application note sllimm? small low-loss intelligent molded module by carmelo parisi and giovanni tomasello introduction in recent years the variable speed motor control market has required high performance solutions able to satisfy the increasing energy saving requirements, compactness, reliability, and system costs in home appliances, such as washing machines, dish washers, refrigerators, air conditioning compressor drives, and in low power industrial applications, such as sewing machines, pumps, tools, etc. to meet these market needs, stmicroelectronics has developed a new family of compact, high efficiency, dual-in-line intelligent power modules, with optional extra features, called small low-loss intelligent molded module (sllimm?). the sllimm product family combines optimized silicon chips, integrated in three main inverter blocks: ? power stage ? six short-circuit rugged igbts ? six freewheeling diodes ? driving network ? three high voltage gate drivers ? discrete gate resistors ? three bootstrap diodes ? protection and optional features ? op amps for advanced current sensing ? comparators for fault protection against overcurrent and short-circuit ? ntc sensor for temperature control ? smart shutdown function ? dead time, interlocking function and undervoltage lockout. thanks to the state of art dbc mounting technology, the fully isolated sllimm package (sdip) offers extremely low thermal resistance with optimum cost-effectiveness and quality level. compared to discrete-based inverters, including power devices, and driver and protection circuits, the sllimm family provides a high integrated level that means simplified circuit design, reduced component count, smaller weight, and high reliability. the aim of this application note is to provide a detailed description of sllimm products, providing guidelines to motor drive designers for an efficient, reliable, and fast design when using the new st sllimm family. www.st.com
contents AN3338 2/72 doc id 18441 rev 4 contents 1 inverter design concept and sllimm solution . . . . . . . . . . . . . . . . . . . . 6 1.1 product synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 product line-up and nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3 internal circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 1.4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 electrical characteristics and functions . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1 igbts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 freewheeling diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3 high voltage gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.1 logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.2 high voltage level shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.3 undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.4 dead time and interlocking function management . . . . . . . . . . . . . . . . . 22 2.3.5 comparators for fault sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.6 short-circuit protection and smart shutdown function . . . . . . . . . . . . . . 25 2.3.7 timing chart of short-circuit protection and smart shutdown function . . 26 2.3.8 current sensing shunt resistor selection . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3.9 rc filter network selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3.10 overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.3.11 op amps for advanced current sensing . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.12 bootstrap circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.3.13 bootstrap capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.3.14 initial bootstrap capacitor charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.1 dbc substrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.2 pcb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3 package structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.4 package outline and dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.5 input and output pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4 power losses and dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 doc id 18441 rev 4 3/72 AN3338 contents 72 4.1 conduction power losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.2 switching power losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.3 thermal impedance overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.4 power losses calculation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5 design and mounting guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.1 layout suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.1.1 general suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.2 mounting instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.2.1 heatsink mounting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.2.2 mounting torque . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.2.3 general handling precaution and storage notices . . . . . . . . . . . . . . . . . 68 6 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 list of tables AN3338 4/72 doc id 18441 rev 4 list of tables table 1. sllimm line-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2. inverter part of stgipl14k60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3. control part of stgipl14k60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. supply voltage and operation behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5. total stgipl14k60 system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6. integrated pull-up/down resistor values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 table 7. interlocking function truth table of stgips10k60a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8. interlocking function truth table of stgips14k60, stgipl14k60, stgips20k60, and st- gipl20k6023 table 9. sdip-25l mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 10. sdip-38l mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 11. input and output pins of sdip-25l package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 12. input and output pins of sdip-38l package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 13. rc cauer thermal network elements by device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 14. mounting torque and heatsink flatness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 table 15. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 doc id 18441 rev 4 5/72 AN3338 list of figures 72 list of figures figure 1. inverter motor drive block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. discrete-based inverter vs. sllimm solution comparison . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. sllimm block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. sllimm nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. internal circuit of stgips10k60a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. internal circuit of stgips14k60 and stgips20k60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7. internal circuit of stgipl14k60 and stgipl20k60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8. stray inductance components of output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 9. high voltage gate drive die image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 10. high voltage gate driver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 11. logic input configuration for stgips10k60a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 12. logic input configuration for stgips14k60, stgipl14k60, stgips20k60, and st- gipl20k60 20 figure 13. timing chart of undervoltage lockout function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 14. timing chart of dead time function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 15. smart shutdown equivalent circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 16. timing chart of smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 figure 17. examples of sc protection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 18. example of sc event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 19. ntc resistance vs. temperature curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 figure 20. example of overtemperature protection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 21. 3-phase system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 22. general advanced current sense scheme and waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 23. bootstrap circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 24. bootstrap capacitor vs. switching frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 25. initial bootstrap charging time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 26. dcb structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 27. pcb structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 28. images and internal view of sdip-25l package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 29. images and internal view of sdip-38l package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 30. outline drawing of sdip-25l package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 figure 31. outline drawing of sdip-38l package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 figure 32. pinout of sdip-25l package (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 33. pinout of sdip-38l package (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 34. typical igbt power losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 35. igbt and diode approximation of the output characteristics . . . . . . . . . . . . . . . . . . . . . . . 54 figure 36. typical switching waveforms of stgipl14k60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 37. equivalent thermal circuit with heatsink single igbt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 38. thermal impedance curves (stgips14k60 and stgipl14k60) . . . . . . . . . . . . . . . . . . . 59 figure 39. thermal impedance rc cauer thermal network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 40. maximum ic(rms) current vs. f sw simulated curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 41. general suggestions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 42. general suggestions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 43. example 1 of a possible wrong layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 44. example 2 of a possible wrong layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 45. recommended silicon grease thickness and positioning . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 46. measurement point of cu heatsink flatness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 47. recommended fastening order of mounting screws . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 inverter design concept and sllimm solution AN3338 6/72 doc id 18441 rev 4 1 inverter design concept and sllimm solution motor drive applications, ranging from a few tens of watts to mega watts, are mainly based on the inverter concept thanks to the fact that this solution can meet efficiency, reliability, size, and cost constraints required in a number of markets. as shown in figure 1 , an inverter for motor drive applications is basically composed of a power stage, mainly based on igbts and freewheeling diodes; a driving stage, based on high voltage gate drivers; a control unit, based on microcontrollers or dsps; some optional sensors for protections and feedback signals for controls. the approach of this solution with discrete devices produces high manufacturing costs associated with high reliability risks, bigger size and higher weight, a considerable number of components and the significant stray inductances and dispersions in the board layout. in recent years, the use of intelligent power modules has rapidly increased thanks to the benefits of greater integration levels. the new st sllimm family is able to replace more than 30 discrete devices in a single package. figure 2 shows a comparison between a discrete-based inverter and the sllimm solution, the advantages of sllimm can be easily understood and can be summarized in a significantly improved design time, reduced manufacturing efforts, higher flexibility in a wide range of applications, and increased reliability and quality level. in addition, the optimized silicon chips in both control and power stages and the optimized board layout provide maximized efficiency, reduced emi and noise generation, higher levels of protection, and lower propagation delay time. figure 1. inverter motor drive block diagram gate driver power stage sensors bridge rectifier microcontroller m feedback mains ! - v doc id 18441 rev 4 7/72 AN3338 inverter design concept and sllimm solution 72 1.1 product synopsis the sllimm family has been designed to satisfy the requirements of a wide range of final applications in the range of 300 w - 2.0 kw, such as: ? washing machines ? dish washers ? refrigerators ? air conditioning compressor drives ? sewing machines ? pumps ? tools ? low power industrial applications the main features and integrated functions can be summarized as follows: ? 600 v, 10 - 30 a ratings ? 3-phase igbt inverter bridge including: ? six low-loss and short-circuit protected igbts ? six low forward voltage drop and soft recovery freewheeling diodes ? three control ics for gate driving and protection including: ? smart shutdown function ? comparator for fault protection against overcurrent and short-circuit ? op amps for advanced current sensing ? three integrated bootstrap diodes ? interlocking function ? undervoltage lockout figure 2. discrete-based inverter vs. sllimm solution comparison ! - v easy layout and design reduced emi and noise high quality and reliability improve efficiency advanced pro tection function reduce total system cost pass ive components: diodes resistors capacitors hv gate drivers igbts + fwds sllimm inverter design concept and sllimm solution AN3338 8/72 doc id 18441 rev 4 ? ntc thermistor for temperature monitor ? open emitter configuration for individual phase current sensing ? dbc fully isolated package for enhanced thermal behavior ? isolation voltage rating of 2500 v rms ? several passive components for igbt switching speed optimum setting ? gate driver proper biasing and noise filtering. figure 3 shows the block diagram of sllimm included in the inverter solution the power devices (igbts and freewheeling diodes), incorporated in the half bridge block, are tailored for a motor drive application delivering the greatest overall efficiency, thanks to the optimized trade-off between conduction and switching power losses and very low emi generation, as a result of reduced dv/dt and di/dt. the ic gate drivers have been selected in order to meet two levels of functionality giving the designers more freedom to choose: a basic version which includes the essential features for a cost-effective solution and a fully featured version which provides advanced options for a sophisticated control method. the fully isolated sdip package is available in a 25-lead version (sdip-25l) and 38-lead version (sdip-38l) and offers excellent heat dissipation characteristics, thanks to the state of the art dbc mounting technology, ensuring at the same time, very high voltage isolation rating (2500 v rms ), compact size and high reliability. figure 3. sllimm block diagram ! - v sllimm gate driver gate driver gate driver half bridge ntc temperature monitoring uvlo / dead time level shift bootstrap diode comparator smart shut down op-amp uvlo / dead time level shift bootstrap diode comparator smart shut down op-amp uvlo / dead time level shift bootstrap diode comparator smart shut down op-amp half bridge half bridge bridge rectifier microcontroller m feedback mains doc id 18441 rev 4 9/72 AN3338 inverter design concept and sllimm solution 72 1.2 product line-up and nomenclature table 1. sllimm line-up (1) 1. for additional information and the complete product portfolio, refer to www.st.com/modules. features basic version fully featured version stgips10k60a stgips14k60 stgipl 14k60 stgips20k60 stgipl20k60 voltage (v) 600 600 600 600 600 current @ t c =25 c (a) 10 14 15 18 20 r thjc max. single igbt (c/w) 3.8 3 2.8 2.4 2.2 package type sdip-25l sdip-25l sdip-38l sdip-25l sdip-38l package size (mm) x, y, z 44.4x22.0x5.4 44.4x22.0x5.4 49.6x24.5x5.4 44.4x22.0x5.4 49.6x24.5x5.4 dbc substrate yes yes yes yes yes ntc yes no yes no yes integrated bootstrap diode yes yes yes yes yes sd function no yes yes yes yes comparator for fault protection no yes (1 pin) yes (3 pins) yes (1 pin) yes (3 pins) smart shutdown function no yes yes yes yes op amps for advanced current sensing no no yes no yes interlocking function yes yes yes yes yes undervoltage lockout yes yes yes yes yes open emitter configuration yes (3 pins) yes (3 pins) yes (3 pins) yes (3 pins) yes (3 pins) 3.3 / 5 v input interface compatibility yes yes yes yes yes high side igbt input signal active high active high active high active high active high low side igbt input signal active high active low active low active low active low inverter design concept and sllimm solution AN3338 10/72 doc id 18441 rev 4 figure 4. sllimm nomenclature 6 7 * , 3 / . [ * - , * % 7 ' l r g h 6 / / , 0 0 ? , 3 0 3 d f n d j h / 6 ' , 3 / 6 6 ' , 3 / 1 r p l q d o f x u u h q w , & f x u u h q w d w 7 & ? & 7 h f k q r o r j \ . + + l j k i u h t x h q f \ n + ] : 9 h u \ + l j k i u h t x h q f \ n + ] & 0 h g l x p i u h t x h q f \ n + ] 9 & ( 6 y r o w d j h g l y l g h g e \ 6 s h f l d o i h d w x u h v $ % d v l f y h u v l r q 7 1 7 & r s w l r q + % r w k d f w l y h k l j k l q s x w v l j q d o / 6 l q j o h s k d v h doc id 18441 rev 4 11/72 AN3338 inverter design concept and sllimm solution 72 1.3 internal circuit figure 5. internal circuit of stgips10k60a inverter design concept and sllimm solution AN3338 12/72 doc id 18441 rev 4 figure 6. internal circuit of stgips14k60 and stgips20k60 doc id 18441 rev 4 13/72 AN3338 inverter design concept and sllimm solution 72 1.4 absolute maximum ratings the absolute maximum ratings represent the extreme capability of the device and they can be normally used as a worst limit design condition. it is important to note that the absolute maximum value is given according to a set of testing conditions such us temperature, frequency, voltage, and so on. the device performances can change according to the applied condition. figure 7. internal circuit of stgipl14k60 and stgipl20k60 inverter design concept and sllimm solution AN3338 14/72 doc id 18441 rev 4 the sllimm specifications are described below by using the stgipl14k60 datasheet as an example. please refer to the respective product datasheets for a detailed description of other types. equation 1 ? v pn : supply voltage applied between p-n u , n v , n w ? v pn(surge) : supply voltage (surge) applied between p-n u , n v , n w ? v ces : collector emitter voltage the power stage of sllimm is based on igbts (and freewheeling diodes) having 600 v v ces rating. considering the sllimm internal stray inductances during the commutations, which can generate up to 100 v of surge voltage, the maximum surge voltage between p-n (v pn(surge) ) allowed is 500 v. at the same time, the maximum supply voltage (in steady- state) applied between p-n (v pn ) allowed is 450 v because of an additional 50 v of surge voltage generated by the stray inductance between the sllimm and the dc-link capacitor. figure 8 shows the parasitic inductances of the output stage. it is possible to note that there are two major components, the first is due to the internal layout of sllimm, while the second is due to the layout of the board. table 2. inverter part of stgipl14k60 symbol parameter value unit v pn supply voltage applied between p-n u , n v , n w 450 v v pn(surge) supply voltage (surge) applied between p-n u , n v , n w 500 v v ces collector emitter voltage (v in (1) =0) 600 v i c (2) each igbt continuous collector current at t c =25 c 15 a i c (3) each igbt pulsed collector current 30 a p tot each igbt total dissipation at t c =25 c 44 w t scw short-circuit withstand time, v ce =0.5 v (br)ces , t j =125 c, v cc =v boot =15 v, v in (1) =05 v 5s 1. applied between hin u , hin v , hin w ; lin u , lin v , lin w and gnd. 2. calculated according to the iterative equation 1 . 3. pulse width limited by max. junction temperature. )) t ( i t (@ v r t t ) t ( i c c max, j )(max) sat ( ce ) c j ( th c max j c c ? ? = ? doc id 18441 rev 4 15/72 AN3338 inverter design concept and sllimm solution 72 ? i c : each igbt continuous collector current the allowable dc current continuously flowing at collector electrode (t c = 25 c). the i c parameter is calculated according to equation 1 . ? t scw : short-circuit withstand time the igbts incorporated inside the sllimm are tailored for a motor control application, therefore, short-circuit self-protection is one of the main module features. t scw represents the short-circuit, non-repetitive, withstand time. if the short-circuit conditions exceed the above specifications, the lifetime of the device is drastically shortened. it is strongly recommended that the sllimm should not be operated under these conditions. figure 8. stray inductance components of output stage ! - v parasitic inductance due to pcb layout 3 1 8 9 : hvic sllimm to motor 9 e x v 9 e x v parasitic inductance due to the sllimm internal layout the real voltage over the igbt can exceed the rating voltage due to di/dt value and parasitic inductance the over-voltage spike can appear on the sllimm pins v pn(surge) high di/dt value flat v pn value v pn & inverter design concept and sllimm solution AN3338 16/72 doc id 18441 rev 4 ? v cc : low voltage power supply v cc represents the supply voltage of the control part. a local filtering is recommended to enhance the sllimm noise immunity. generally, the use of one electrolytic capacitor (with a greater value but not negligible esr) and a good quality (low esr, low esl) filter capacitor (hundreds of nf), faster than the electrolytic one to provide current, is suggested. small filter capacitors are already connected inside the sllimm, directly on the involved pins (see internal circuits figure 5 , 6 , and 7 ). please refer to ta ble 4 in order to properly drive the sllimm. table 3. control part of stgipl14k60 symbol parameter value unit v out output voltage applied between out u , out v , out w , and gnd (v cc =15 v) v boot -21 to v boot +0.3 v v cc low voltage power supply -0.3 to 21 v v cin comparator input voltage -0.3 to v cc +0.3 v v boot bootstrap voltage -0.3 to 620 v v in logic input voltage applied between hin, lin and gnd -0.3 to 15 v v sd /od open drain voltage -0.3 to 15 v dv out /dt allowed output slew rate 50 v/ns table 4. supply voltage and operation behavior v cc voltage (typ. value) (1) operating behavior < 12 v as the voltage is lower than the uvlo threshold the control circuit is not fully turned on. a perfect functionality cannot be guaranteed. 12 v ? 13.5 v igbts can work, however conduction and switching losses increase due to low voltage gate signal. 13.5 v ? 18 v recommended value (see relevant datasheets). 18 v ? 21 v igbts can work. switching speed is faster and saturation current higher, increasing short-circuit broken risk and emi issues. > 21 v control circuit is destroyed. absolute max. rating is 21 v. 1. except for stgips10k60a. for further information please refer to the relevant datasheet. table 5. total stgipl14k60 system symbol parameter value unit v iso isolation withstands voltage applied between each pin and heatsink plate (ac voltage, t = 60 sec.) 2500 v t j operating junction temperature -40 to 150 c t c module case operation temperature -40 to 125 c doc id 18441 rev 4 17/72 AN3338 electrical characteristics and functions 72 2 electrical characteristics and functions in this section the main electrical characteristics of the power stage are discussed, together with a detailed description of all the sllimm functions. 2.1 igbts the sllimm achieves power savings in the inverter stage thanks to the use of igbts manufactured with the proprietary advanced powermesh? process. these power devices, optimized for the typical motor control switching frequency, offer an excellent trade-off between voltage drop (v ce(sat) ) and switching speed (t fall ), and therefore minimize the two major sources of energy loss, conduction and switching, reducing the environmental impact of daily-use equipment. a full analysis on the power losses of the complete system is reported in section 4: power losses and dissipation . this igbt family is capable of surviving short-circuits lasting up to 5 microseconds, as expected by targeted applications. 2.2 freewheeling diodes the turbo 2 ultrafast high voltage diodes have been adequately selected for the sllimm family and carefully tuned to achieve the best t rr /v f trade-off and softness as freewheeling diodes in order to further improve the total performance of the inverter and significantly reduce the electromagnetic interference (emi) in motor control applications which are quite sensitive to this phenomena. 2.3 high voltage gate drivers the sllimm is equipped with a versatile high voltage gate driver ic (hvic), designed using bcd offline (bipolar, cmos, and dmos) technology (see figure 9 ) and particularly suited to field oriented control (foc) motor driving applications, able to provide all the functions and current capability necessary for high side and low side igbt driving. this driver can be used in all applications where high voltage shifted control is necessary and it includes a patented internal circuitry which replaces the external bootstrap diode. each high voltage gate driver chip controls two igbts in half bridge topology, offering the basic functions such as dead time, interlocking, integrated bootstrap diode, and also the advanced features such as smart shutdown (patented), fault comparator, and a dedicated high performance op amp for advanced current sensing. a schematic summary of the features by device are listed in table 1 . in this application note the main characteristics of a high voltage gate drive related to the sllimm are discussed. for a greater understanding, please refer to the an2738 application note. electrical characteristics and functions AN3338 18/72 doc id 18441 rev 4 figure 9. high voltage gate drive die image figure 10. high voltage gate driver block diagram ! - v uv detection p n v boot out v ref cin hvic + +5v from lvg uv detection from c from c from/to c sd/od lin hin v cc gnd dt op out smart shut down + +5v +5v v cc v cc dead time to adc v cc v cc logic shoot- trough prevention shutdown latch level shifter uv detection s r floating structure lvg driver hvg driver bootstrap driver bootstrap driver c boot v bias hvg lv g boot sllimm to motor r shunt op+ op- r sf c sf cp+ u,v,w v bias c df r df v cc to dc-link r sd c sd + - comp + - op-amp doc id 18441 rev 4 19/72 AN3338 electrical characteristics and functions 72 2.3.1 logic inputs the high voltage gate driver ic has two logic inputs, hin and lin, to separately control the high side and low side outputs, hvg and lvg. please refer to table 1 for the input signal logics by device. in order to prevent any cross conduction between high side and low side igbt a safety time (dead time) is introduced (see section 2.3.4: dead time and interlocking function management for further details). all the logic inputs are provided with hysteresis (~1 v) for low noise sensitivity and are ttl/cmos 3.3 v compatible. thanks to this low voltage interface logic compatibility, the sllimm can be used with any kind of high performance controller, such as microcontrollers, dsps or fpgas. as shown in the block diagrams of figure 11 and figure 12 , the logic inputs have internal pull-down (or pull-up) resistors in order to set a proper logic level in case of interruption in the logic lines. if logic inputs are left floating, the gate driver outputs lvg and hvg are set to low level. this simplifies the interface circuit by eliminating the six external resistors and, therefore saving cost, board space and number of components. figure 11. logic input confi guration for stgips10k60a ! - v hvic sllimm 3 1 9 % 2 2 7 9 & & 2 8 7 / , 1 + , 1 high side le vel shifting dri ver low side dri ver uv detection uv detection logic sho ot-trough pre vention bootstrap driver electrical characteristics and functions AN3338 20/72 doc id 18441 rev 4 the typical values of the integrated pull-up/down resistors are shown in table 6 : figure 12. logic input configuration for st gips14k60, stgipl14k60, stgips20k60, and stgipl20k60 ! - v p n v boot v cc out hin high side le vel shifting dri ver low side dri ver uv detection uv detection logic sho ot-trough prevention shu tdown lin lin sd smart sd v ref + - cin bootstrap driver hvic sllimm +5v table 6. integrated pull-up/down resistor values input pin pn input pin logic internal pull-up internal pull-down high side gate driving hin u , hin v , hin w stgips10k60a active high 500 k low side gate driving lin u , lin v , lin w stgips10k60a active high 500 k high side gate driving hin u , hin v , hin w stgips14k60 stgipl14k60 stgips20k60 stgipl20k60 active high 85 k low side gate driving lin u , lin v , lin w stgips14k60 stgipl14k60 stgips20k60 stgipl20k60 active low 720 k sd / od shutdown stgips14k60 stgipl14k60 stgips20k60 stgipl20k60 active low 125 k doc id 18441 rev 4 21/72 AN3338 electrical characteristics and functions 72 2.3.2 high voltage level shift the built-in high voltage level shift allows direct connection between the low voltage control inputs and the high voltage power half bridge in any power application up to 600 v. it is obtained thanks to the bcd offline technology which integrates, in the same die bipolar devices, low and medium voltage cmos for analog and logic circuitry and high voltage dmos transistors with a breakdown voltage in excess of 600 v. this key feature eliminates the need for external optocouplers, resulting in significant savings regarding component count and power losses. other advantages are high-frequency operation and short input-to- output delays. 2.3.3 undervoltage lockout the sllimm supply voltage v cc is continuously monitored by an undervoltage lockout (uvlo) circuitry which turns off the gate driver outputs when the supply voltage goes below the v cc_thoff threshold specified on the datasheet and turns on the ic when the supply voltage goes above the v cc_thon voltage. a hysteresis of about 1.5 v is provided for noise rejection purposes. the high voltage floating supply v boot is also provided with a similar undervoltage lockout circuitry. when the driver is in uvlo condition, both gate driver outputs are set to low level, setting the half bridge power stage output to high impedance. the timing chart of undervoltage lockout, plotted in figure 13 , is based on the following steps: ? t1: when the v cc supply voltage raises the v cc_thon threshold, the gate driver starts to work after the next input signal hin/lin is on. the circuit state becomes reset. ? t2: input signal hin/lin is on and the igbt is turned on. ? t3: when the v cc supply voltage goes below the v cc_thoff threshold, the uvlo event is detected. the igbt is turned off in spite of input signal hin/lin. the state of the circuit is now set. ? t4: the gate driver re-starts once the v cc supply voltage again raises the v cc_thon threshold. ? t5: input signal hin/lin is on and the igbt is turned on again. electrical characteristics and functions AN3338 22/72 doc id 18441 rev 4 2.3.4 dead time and inte rlocking function management in order to prevent any possible cross-conduction between high side and low side igbts, the sllimm provides both the dead time and the interlocking functions. the interlocking function is a logic operation which sets both the outputs to low level when the inputs are simultaneously active. the dead time function is a safety time introduced by the device between the falling edge transition of one driver output and the rising edge of the other output. if the rising edge set externally by the user occurs before the end of this dead time, it is ignored and results as delayed until the end of the dead time. the dead time is internally set at 320 ns as the typical value of stgips10k60a. figure 13. timing chart of undervoltage lockout function ! - v time t2 t3 t4 reset circuit state t1 set reset v cc_thon t5 v cc_thoff i c v cc hin/lin table 7. interlocking function truth table of stgips10k60a condition logic input (v i ) outputs lin hin lvg hvg interlocking half bridge tri-state hhl l 0 ?logic state? half bridge tri-state llll 1 ?logic state? low side direct driving hlhl 1 ?logic state? high side direct driving lhlh doc id 18441 rev 4 23/72 AN3338 electrical characteristics and functions 72 note: x: not important. the dead time is internally set at 600 ns as typical value. in figure 14 the details of dead time and interlocking function management of the stgips14k60, stgipl14k60, stgips20k60, and stgipl20k60 products are described. table 8. interlocking function truth table of stgips14k60, stgipl14k60, stgips20k60, and stgipl20k60 condition logic input (v i ) outputs sd lin hin lvg hvg shutdown enable half bridge tri-state lxxll interlocking half bridge tri-state hlhll 0 ?logic state? half bridge tri-state hhlll 1 ?logic state? low side direct driving hllhl 1 ?logic state? high side direct driving hhhlh electrical characteristics and functions AN3338 24/72 doc id 18441 rev 4 2.3.5 comparators for fault sensing the sllimm family integrates up to three comparators (with reference to the product line-up in ta ble 1 ) intended for advanced fault protection, such as overcurrent, overtemperature or any other type of fault measurable via a voltage signal. each comparator has an internal reference voltage v ref , specified in the datasheet, on its inverting input (see figure 10 ), while the non-inverting input is available on c in pins (one per half bridge). the comparators input can be connected to an external shunt resistor, in order to implement a simple overcurrent or short-circuit detection function, as discussed in detail in section 2.3.6: short- circuit protection and smart shutdown function . nevertheless, in the case of three internal comparators, they can be separately used in order to implement three independent controls. figure 14. timing chart of dead time function / , 1 + , 1 / 9 * + 9 * / , 1 + , 1 / 9 * + 9 * / , 1 + , 1 / 9 * + 9 * / , 1 + , 1 / 9 * + 9 * ' 7 / + ' 7 + / ' 7 / + ' 7 + / ' 7 / + ' 7 + / ' 7 / + ' 7 + / j d w h g u l y h u r x w s x w v 2 ) ) + $ / ) % 5 , ' * ( 7 5 , 6 7 $ 7 ( * / 5 & 3 - 0 $ , * / ( * / 5 & 3 - 0 $ , * / ( & 2 1 7 5 2 / 6 , * 1 $ / ( ' * ( 6 2 9 ( 5 / $ 3 3 ( ' , 1 7 ( 5 / 2 & . , 1 * ' ( $ ' 7 , 0 ( & 2 1 7 5 2 / 6 , * 1 $ / 6 ( ' * ( 6 6 < 1 & + 5 2 1 2 8 6 ' ( $ ' 7 , 0 ( & 2 1 7 5 2 / 6 , * 1 $ / 6 ( ' * ( 6 1 2 7 2 9 ( 5 / $ 3 3 ( ' % 8 7 , 1 6 , ' ( 7 + ( ' ( $ ' 7 , 0 ( ' ( $ ' 7 , 0 ( & 2 1 7 5 2 / 6 , * 1 $ / 6 ( ' * ( 6 1 2 7 2 9 ( 5 / $ 3 3 ( ' 2 8 7 6 , ' ( 7 + ( ' ( $ ' 7 , 0 ( ' , 5 ( & 7 ' 5 , 9 , 1 * * / 5 & 3 - 0 $ , * / ( * / 5 & 3 - 0 $ , * / ( ( j d w h g u l y h u r x w s x w v 2 ) ) + $ / ) % 5 , ' * ( 7 5 , 6 7 $ 7 ( j d w h g u l y h u r x w s x w v 2 ) ) + $ / ) % 5 , ' * ( 7 5 , 6 7 $ 7 ( j d w h g u l y h u r x w s x w v 2 ) ) + $ / ) % 5 , ' * ( 7 5 , 6 7 $ 7 ( j d w h g u l y h u r x w s x w v 2 ) ) + $ / ) % 5 , ' * ( 7 5 , 6 7 $ 7 ( j d w h g u l y h u r x w s x w v 2 ) ) + $ / ) % 5 , ' * ( 7 5 , 6 7 $ 7 ( j d w h g u l y h u r x w s x w v 2 ) ) + $ / ) % 5 , ' * ( 7 5 , 6 7 $ 7 ( j d w h g u l y h u r x w s x w v 2 ) ) + $ / ) % 5 , ' * ( 7 5 , 6 7 $ 7 ( doc id 18441 rev 4 25/72 AN3338 electrical characteristics and functions 72 2.3.6 short-circuit protecti on and smart shutdown function the sllimm is able to monitor the output current and provide protection against overcurrent and short-circuit conditions in a very short time (comparator triggering to high/low side driver turn-off propagation delay t isd = 200 ns), thanks to the smart shutdown function. this feature is based on an innovative patented circuitry which provides an intelligent fault management operation and greatly reduces the protection intervention delay independently on the protection time duration which can be set as desired by the device user. as already mentioned in section 2.3.5: comparators for fault sensing and shown in figure 10 , each comparator input can be connected to an external shunt resistor, r shunt , in order to implement a simple overcurrent detection function. an rc filter network (r sf and c sf ) is necessary to prevent erroneous operation of the protection. the output signal of the comparators is fed to an integrated mosfet with the open drain available on the sd /od pin, shared with the sd input. when the comparator triggers, the device is set in shutdown state and all its outputs are set to low level, leaving the half bridge in tri-state. in common overcurrent protection architectures, usually the comparator output is connected to the sd input and an external rc network (r sd and c sd ) is connected to this sd /od line in order to provide a mono-stable circuit which implements a protection time when a fault condition occurs. contrary to common fault detection systems, the new smart shutdown structure allows to immediately turn off the output gate driver in the case of fault, without waiting for the external capacitor to be discharged. this strategy minimizes the propagation delay between the fault detection event and the actual outputs switch off. in fact, the time delay between the fault and outputs disabling is not dependent on the rc value of the external sd circuitry but, thanks to the new architecture, has a preferential path internally in the driver. then the device immediately turns off the driver outputs and latches the turn-on of the open drain switch, until the sd signal has reached its lower threshold. after the sd signal goes below the lower threshold, the open drain is switched off (see figure 16 ). the smart shutdown system provides the possibility to increase the value of the external rc network across the sd pin (sized to fix the disable time generated after the fault event) as much as desired by the user without compromising the intervention time delay of the sllimm protection. a block diagram of the smart shutdown architecture is depicted in figure 15 . electrical characteristics and functions AN3338 26/72 doc id 18441 rev 4 in normal operation the outputs follow the commands received from the respective input signals. when a fault detection event occurs, the fault signal (fsd) is set to high by the fault detection circuit output and the ff receives a set input signal. consequently, the ff outputs set the sllimm output signals to low level and, at the same time, turn on the open drain mosfet which works as active pull-down for the sd signal. note that the gate driver outputs stay at low level until the sd pin has experienced both a falling edge and a rising edge, although the fault signal could be returned to low level immediately after the fault sensing. in fact, even if the ff is reset by the falling edge of the sd input, the sd signal also works as enable for the outputs, thanks to the two and ports. moreover, once the internal open drain transistor has been activated, due to the latch, it cannot be turned off until the sd pin voltage reaches the low logic level. note that, since the ff is set dominant, oscillations of the sd pin are avoided if the fault signal remains steady at high level. 2.3.7 timing chart of short-circuit protection and smart shutdown function with reference to figure 16 , the short-circuit protection is based on the following steps: ? t1: when the output current is lower than the max. allowed level, the sllimm is working in normal operation. ? t2: when the output current reaches the max. allowed level (i sc ), the overcurrent/short- circuit event is detected and the protection is activated. the voltage across the shunt resistor, and then on the c in pin, exceeds the v ref value, the comparator triggers, setting the device in shutdown state and both its outputs are set to low level leading the half bridge to tri-state. the smart shutdown switches off the igbt gate (hvg, lvg) through a preferential path (200 ns as typical internal delay time) and, at the same time, it switches on the m1 internal mosfet. the sd signal starts the discharge phase and its value drops with a time constant a . the time constant a value is given by: figure 15. smart shutdown equivalent circuitry ! - v v ref hvic + set dominant ff lv g hvg sllimm cp+ + - comp fsd hin lin sd v bias except for stgips10k60a q s q r doc id 18441 rev 4 27/72 AN3338 electrical characteristics and functions 72 equation 2 ? t3: the sd signal reaches the lower threshold v sd_l_thr and the control unit switches off the input hin and lin. the smart shutdown is disabled (m1 off) and sd can rise up with a time constant b , given by: equation 3 ? t4: when the sd signal reaches the upper threshold v sd_h_thr , the system is re- enabled. 2.3.8 current sensing shunt resistor selection as previously discussed, the shunt resistors r shunt externally connected between the n pin and ground (see figure 10 ) are used to realize the overcurrent detection. when the output current exceeds the short-circuit reference level (i sc ), the c in signal overtakes the v ref value and the short-circuit protection is active. for a reliable and stable operation the current sensing resistor should be a high quality, low tolerance non-inductive type. in fact, stray inductance in the circuit, which includes the layout, the rc filter, and also the shunt resistor, must be minimized in order to avoid undesired short-circuit detection. () sd sd od _ on a c r // r ? = ? = figure 16. timing chart of smart shutdown function 7 l p h 7 l p h & r q v w d q w v s z & / ^ w w w 9 v g b + b 7 + 5 9 v g b / b 7 + 5 2 2 2 $ 5 2 1 b 2 ' 5 6 ' & 6 ' 2 % 5 6 ' & 6 ' 6 ' g l v f k d u j h w l p h 6 ' u h f k d u j h w l p h + 9 * / 9 * 9 6 + 8 1 7 9 & , 1 , & 6 ' 0 w 5 & f l u f x l w w l p h f r q v w d q w + , 1 / , 1 i u r p w r & 6 ' 2 ' 0 6 p d u w v k x w g r z q 9 % l d v 5 6 ' & 6 ' 6 / / , 0 0 5 2 1 b 2 ' 6 k x w g r z q f l u f x l w 2 dd 2 electrical characteristics and functions AN3338 28/72 doc id 18441 rev 4 for these reasons, the shunt resistor and the filtering components must be placed as close as possible to the sllimm pins, for additional suggestions refer to section 5.1: layout suggestions . the value of the current sense resistor can be calculated by following different guidelines, functions of the design specifications, or requirements. a common criterion is presented here based on the following steps: ? defining of the overcurrent threshold value (i oc_th ). for example, it can be fixed considering the igbt typical working current in the application and adding 20-30% as overcurrent. ? calculation of the shunt resistor value according to the conditioning network. an example of the conditioning network is shown in figure 22 . further details can be found in the user manuals listed (see references 7 , references 8 , and references 9 ). ? selection of the closest shunt resistor commercial value. ? calculation of the power rating of the shunt resistor, taking into account that this parameter is strongly temperature dependent. therefore, the power derating ratio of the shunt resistor, p(t)%, shown in the manufacturer's datasheet, must be considered in the calculation as follows: equation 4 where i rms is the igbt rms working current. for a proper selection of the shunt resistor, a safety margin of at least 30% is recommended on the calculated power rating. )% t ( p i r ) t ( p 2 rms shunt shunt ? = doc id 18441 rev 4 29/72 AN3338 electrical characteristics and functions 72 2.3.9 rc filter network selection two options of shunt (1- or 3-shunt) resistor circuit can be adopted in order to implement different control technique and short-circuit protection, as shown in figure 17 . a rc filter network is required to prevent undes ired short-circuit operation due to the noise on the shunt resistor. both solutions allow to detect the total current in all three phases of the inverter. the filter is based on the r sf and c sf network and its time constant is given by: equation 5 in addition to the rc time constant, the turn-off propagation delay of the gate driver, t isd (specified in the datasheet) and the igbt turn-off time (in the range of tens of ns), must be considered in the total delay time (t to t a l ), which is the time necessary to completely switch off the igbt once the short-circuit event is detected. therefore, the t to t a l is calculated as follows: equation 6 also considering that the igbt short-circuit withstand time (t sc ) is 5 s, the t sf is recommended to be set in the range of 1~2 s. in the case of a 3-shunt resistors circuit, a specific control technique can be implemented by using the three shunt resistors (r shunt_u , r shunt_v and r shunt_w ) able to monitor each phase current. figure 17. examples of sc protection circuit ! - v sllimm c sf r sf r shunt cin nw nu nv sllimm c sf r sf r shunt cin nw nu nv r shunt_u r shunt_w r shunt_v 1-shunt resistor circuit 3-shunt resistors circuit sf sf sf c r t ? = + + = electrical characteristics and functions AN3338 30/72 doc id 18441 rev 4 an example of a short-circuit event is shown in figure 18 , where it is possible to note the very fast protection, thanks to the smart shutdown function, against fault events. the main steps are: ? t1: collector current i c starts to rise. sc event is not detected yet due to the rc network on the c in pin ? t2: voltage on v cin reaches the v ref . sc event is detected and the smart shutdown starts to turn off the sllimm. ? t3: the sllimm is definitively turned off in less than 300 ns (including the t d(off) time of igbt) from sc detection. finally, the total disable time is t3-t2 and the total sc action time is t3-t1. 2.3.10 overtemperature protection stgips10k60a, stgipl14k60, and stgipl20k60 are equipped with a negative temperature coefficient (ntc) thermistor for an easy overtemperature protection, in the case of slow case temperature drift or just for the temperature measurements, sending this information to the microcontroller in real-time. due to the thermal impedance of sllimm and its own time constant, the ntc thermistor is not suited to detect rapid junction temperature rise of the power devices directly. therefore, it cannot be used for short-circuit or overcurrent protection, but only for slow changes in temperature monitoring. the resistance versus temperature characteristic of ntc thermistor, represented in figure 19 , is non-linear and is described by the following expression: equation 7 figure 18. example of sc event $ 0 y & , 1 + , 1 , & $ ' l y [ + , 1 9 ' l y & , 1 9 ' l y w q v ' l y , & 7 l p h w w w 6 / / , 0 0 3 1 8 9 : 5 6 + 8 1 7 w r p r w r u & , 1 , & 6 & h y h q w r q w k h o r z v l g h , * % 7 w r ' & o l q n ( [ d p s o h r i 6 & h y h q w q v s z & + , 1 + 9 , & ? ? ? ? ? ? ? ? = 298 1 t 1 b 25 e r ) t ( r doc id 18441 rev 4 31/72 AN3338 electrical characteristics and functions 72 where t is the temperature in kelvin, b and r 25 , respectively, are a constant value in the sllimm working range and the resistance value at 25 c, both parameters are shown in the datasheet. an easy circuit, using a voltage divider, for both overtemperature protection and temperature monitoring, is shown in figure 20 : the external comparator is used to send a shutdown signal to the sllimm in case of overtemperature. the v ntc_th is a threshold voltage, fixed by design, and connected on the non inverting input, whilst the inverting input is connected on a voltage divider based on the ntc and r ot resistors. when voltage on the inverting input exceeds the v ntc_th value the comparator triggers, pulling down the sd and, consequently, switching off the igbts. figure 19. ntc resistance vs. temperature curve figure 20. example of overtemperature protection circuit ! - v t1 t2 +v dd ntc sllimm c ot r ot sd v ntc_th + - electrical characteristics and functions AN3338 32/72 doc id 18441 rev 4 for a proper sizing of the voltage divider, first of all the maximum allowed temperature level (t ot_max ) must be fixed, consequently the thermistor resistance is given by equation 7 , as well as by figure 19 . the value of r ot resistance can be calculated by using the voltage divider formula: equation 8 taking into account that, if t = t ot_max then v - (t ot_max ) = v ntc_th . the maximum allowed power on the thermistor should not exceed 50 mw in all the operating range, in order to guarantee a safe working condition and avoid power consumption affecting the temperature meas urement through self-heating. therefore, considering (t = t ot_max ), it must be: equation 9 finally, to increase the noise immunity of the ntc thermistor, it is recommended to parallel a decoupling capacitor (c ot ), whose value must be between 10 to 100 nf. 2.3.11 op amps for advanced current sensing the sllimm devices, in the sdip-38l package, integrate also three operational amplifiers optimized for field oriented control (foc) applications. in a typical foc application the currents in the three half bridges are sensed using a shunt resistor. the analog current information is transformed into a discontinuous sense voltage signal, having the same frequency as the pwm signal driving the bridge. the sense voltage is a bipolar analog signal, whose sign depends on the direction of the current (see figure 21 ): dd ot ntc ot v r ) t ( r r ) t ( v ? + = ? mw 50 r r v r i r 2 ot ntc dd ntc 2 ntc ? ? ? ? ? ? ? ? + ? = ? doc id 18441 rev 4 33/72 AN3338 electrical characteristics and functions 72 the sense voltage signals must be provided to an a/d converter. they are usually shifted and amplified by dedicated op amps in order to exploit the full range of the a/d converter. the typical scheme and principle waveforms are shown in figure 22 : figure 21. 3-phase system 3-phase driver sinusoidal vector control sensing: discontinuous voltage at f pwm frequency 9 6 9 6 9 6 discontinuous voltage at f pwm frequency power stage s k d v h p r w r u i phase am09338v1 figure 22. general advanced current sense scheme and waveforms 9 v h q v h + d o i e u l g j h f x u u h q w v h q v l q j 9 r o w d j h v k l i w l q j r i w k h 9 v h q v h 6 h q v h y r o w d j h v l j q d o 6 k l i w h g d q g f h q w h u h g v l j q d o $ p s o l i l h g v l j q d o ) l o w h u h g v l j q d o 9 r o w d j h j d l q d q g i l o w h u l q j 5 2 8 7 u h t x l u h g w r p d n h w k h r s d p s v w d e o h & 2 8 7 u h t x l u h g e \ w k h $ ' & i r u v d p s o l q j s x u s r v h 9 5 ( ) 5 6 + 8 1 7 2 3 & 2 8 7 & 5 5 5 5 2 3 5 2 8 7 2 s d p s 5 w r p r w r u w r ' & o l q n w r $ ' & electrical characteristics and functions AN3338 34/72 doc id 18441 rev 4 adcs used in vector control applications have a typical full scale range (fsr) of about 3.3 v. the sense signals must be shifted and centered on fsr/2 voltage (about 1.65 v) and amplified with a gain which provides the matching between the maximum value of the sensed signal and the fsr of the adc. some typical examples of sense network sizing can be found in the user manuals listed (see references 7 , references 8 , and references 9 ). 2.3.12 bootstrap circuit in the 3-phase inverter the emitters of the low side igbts are connected to the negative dc bus (v dc- ) as common reference ground, which allows all low side gate drivers to share the same power supply, while, the emitter of high side igbts is alternately connected to the positive (v dc+ ) and negative (v dc- ) dc bus during the running conditions. a bootstrap method is a simple and cheap solution to supply the high voltage section. this function is normally accomplished by a high voltage fast recovery diode. the sllimm family includes a patented integrated structure that replaces the external diode. it is realized with a high voltage dmos driven synchronously with the low side driver (lvg) and a diode in series. an internal charge pump provides the dmos driving voltage. the operation of the bootstrap circuit is shown in figure 23 . the floating supply capacitor c boot is charged, from the v cc supply, when the v out voltage is lower than the v cc voltage (e.g. low side igbt is on), through the bootstrap diode and the dmos path with reference to the ?bootstrap charge current path?. during the high side igbt on phase, the bootstrap circuit provides the right gate voltage to properly drive the igbt (see ?bootstrap discharge current path?). this circuit is iterated for all three half bridges. figure 23. bootstrap circuit / h j h q g & % 2 2 7 2 8 7 + 9 * 9 e r r w / 9 * 3 1 8 9 : ' 0 2 6 9 e r r w 9 & & * 1 ' / , 1 2 8 7 9 & & 6 / / , 0 0 e r r w v w u d s g l r g h f k d u j h s x p s + 9 , & % r r w v w u d s f k d u j h f x u u h q w s d w k % r r w v w u d s g l v f k d u j h f x u u h q w s d w k doc id 18441 rev 4 35/72 AN3338 electrical characteristics and functions 72 the value of the c boot capacitor should be calculated according to the application condition and must take the following into account: ? voltage across c boot must be maintained at a value higher than the undervoltage lockout level for the ic driver. this enables the high side igbt to work with a correct gate voltage (lower dissipation and better overall performances). bear in mind that if a voltage below the uvlo threshold is applied on the bootstrap channel, the ic disables itself (no output) without any fault signal. ? the voltage across c boot is affected by different components such as drop across the integrated bootstrap structure, drop across the low side igbt, and others. ? when the high side igbt is on, the c boot capacitor discharges mainly to provide the right igbt gate charge but other phenomena must be considered such as leakage currents, quiescent current, etc. 2.3.13 bootstrap capacitor selection a simple method to properly size the bootstrap capacitor considers only the amount of charge that is needed when the high voltage side of the driver is floating and igbt gate is driven once. this approach does not take into account either the duty cycle of the pwm, or the fundamental frequency of the current. during the bootstrap capacitor charging phase, the low side igbt is on and the voltage across c boot (v cboot ) can be calculated as follows: equation 10 where: v cc : supply voltage of gate driver v f : bootstrap diode forward voltage drop v ce(sat)max : maximum emitter collector voltage drop of low side igbt v rds(on) : dmos voltage drop the dimension of the bootstrap capacitance c boot value is based on the minimum voltage drop ( v cboot ) to guarantee when the high side igbt is on, and must be: equation 11 under the condition: equation 12 where: v ge(min) : minimum gate emitter voltage of high side igbt v bs_thon : bootstrap turn-on undervoltage threshold (maximum value, see datasheet) max ) sat ( ce ) on ( rds f cc cboot v v v v v ? ? ? = max ) sat ( ce (min) ge ) on ( rds f cc cboot v v v v v v ? ? ? ? = thon _ bs (min) cboot v v > electrical characteristics and functions AN3338 36/72 doc id 18441 rev 4 considering the factors contributing to v cboot decreasing, the total charge supplied by the bootstrap capacitor (during high side on phase) is: equation 13 where: q gate : total igbt gate charge i lkge : igbt gate emitter leakage current i qbo : bootstrap circuit quiescent current i lk : bootstrap circuit leakage current i lkdiode : bootstrap diode leakage current i lkcap : bootstrap capacitor leakage current (relevant when using an electrolytic capacitor but can be ignored if other types of capacitors are used) t hon : high side on time q ls : charge required by the internal level shifters finally, the minimum size of the bootstrap capacitor is: equation 14 for an easier selection of bootstrap capacitor, figure 24 shows the behavior of c boot (calculated) versus switching frequency (f sw ), with different values of v cboot , corresponding to equation 14 for a continuous sinusoidal modulation and for stgips20k60 and stgipl20k60 (worst case) and a duty cycle = 50%. for all the other devices the bootstrap capacitor can be calculated using the same curve. () ls hon ap lkc lkdiode lk qbo lkge ga te to t q t i i i i i q q + ? + + + + + = cboot tot boot v q c = doc id 18441 rev 4 37/72 AN3338 electrical characteristics and functions 72 considering the limit cases during the pwm control and further leakages and dispersions in the board layout, the capacitance value to use in the bootstrap circuit must be selected two or three times higher than the c boot calculated in the graph of figure 24 . the bootstrap capacitor should be with a low esr value for a good local decoupling, therefore, in case an electrolytic capacitor is used, a good quality (low esr, low esl) filter capacitor placed directly on the sllimm pins is strictly recommended. 2.3.14 initial bootstrap capacitor charging during the startup phase, the bootstrap capacitor must be charged for a suitable time to complete the initial charging time (t charge ), which is, at least, the time v cboot needs to exceed the turn-on undervoltage threshold v bs_thon , as already stated in equation 12 . for a normal operation, the voltage across the bootstrap capacitor must never drop down to the turn-off undervoltage threshold v bs_thoff throughout the working conditions. for the period of startup, only the low side igbt is switched on and, just after this phase, the pwm is run, as shown in the following steps of figure 25 : ? t1: the bootstrap capacitor starts to charge through the low side igbt (lvg) ? t2: the voltage across the bootstrap capacitor (v cboot ) reaches its turn-on undervoltage threshold v bs_thon . ? t3: the bootstrap capacitor is fully charged, this enables the high side igbt and the c boot capacitor starts to discharge in order to provide the right igbt gate charge. the bootstrap capacitor recharges during the on state of low side igbt (lvg). figure 24. bootstrap capacitor vs. switching frequency am09341v1 0 1 2 3 4 5 0 5 10 15 20 f sw (khz) c boot calculated (f) stgipx20k60 =50% v cb oot =0.1v v cboot =0.3v v cboot =0.5v electrical characteristics and functions AN3338 38/72 doc id 18441 rev 4 the initial charging time is given by equation 15 and must be, for safety reasons, at least three times longer than the calculated value. equation 15 where is the duty cycle of the pwm signal and r ds(on) is 120 typical value, as shown in the datasheet. a practical example can be done by considering a motor drive application where the pwm switching frequency is 12.5 khz, with a duty cycle of 50%, and v cboot = 0.1 v (that means, a gate driver supply voltage v cc = 17.6 v). from the graph in figure 24 the bootstrap capacitance is 1.5 f, therefore, the c boot can be selected by using a value between 3.0 and 4.5 f. according to the commercial value the bootstrap capacitor can be 3.3 f. from equation 15 , the initial charging time is: equation 16 for safety reasons, the initial charging time must be at least 12 ms. figure 25. initial bootstrap charging time ! - v time v cboot t1 lvg v cc dc bus v pn v bs_thon t3 t2 hvg v bs_thoff ? ? ? ? ? ? ? ? ? cboot cc ) on ( ds boot charge v v ln * r c t ms 4 1 . 0 6 . 17 ln 5 . 0 120 10 3 . 3 t 6 charge = ? ? ? ? ? ? ? ? ? ? ? ? doc id 18441 rev 4 39/72 AN3338 package 72 3 package the sllimm benefits from a compact package while providing high power density, the best thermal performance, and great electrical isolation (> 2500 v rms ). the sdip is a dual-in-line transfer mold pa ckage, available in 25-lead version (sdip-25l) and 38-lead version (sdip-38l) and based on the state of the art dbc mounting technology for the power stage, whilst the control stage is assembled on a pcb layer. a vacuum soldering process is used to avoid any gas inclusion (voids) during the soldering process that could cause potential hot spots. it results in a further increase in the reliability of the sllimm family due to the improved thermal and electrical conductivity. this technology makes it possible to achieve extremely low thermal resistance values, high stability in thermal cycling, small size with optimum cost-effectiveness, and quality level. 3.1 dbc substrate dbc means direct bonded copper and denotes a process in which copper and a ceramic material are directly bonded, as shown in figure 26 . direct bonded copper substrates have been proven for many years to be an excellent solution for electrical isolation and thermal management of high power semiconductor modules. the advantages of dbc substrates are, firstly, high current-carrying capability, due to thick copper metallization, and secondly, a thermal expansion coefficient close to the silicon one at the copper surface. dbc has two layers of copper that are directly bonded onto an aluminum-oxide (al 2 o 3 ) ceramic base. the dbc process yields a super-thin base and eliminates the need for thick, heavy copper bases that were used prior to this process. because sllimm with dbc bases has fewer layers, it has much lower thermal resistance values than those based on different materials. figure 26. dcb structure package AN3338 40/72 doc id 18441 rev 4 the main properties of dbc ceramic substrates the main properties of dbc include good mechanical strength, mechanically stable shape, good adhesion and corrosion resistance, and also offer: ? excellent electrical isolation ? very good thermal conductivity ? the thermal expansion coefficient is close to that of silicon, so no interface layers are required ? good heat spreading ? may be structured just like printed circuit boards or ?ims substrates? ? environmentally clean 3.2 pcb a pcb (printed circuit board) is used to mech anically support the gate driver ics and to electrically connect those using conductive pathways. thanks to the internal pcb it is possible to realize various electric configurations, necessary to add advanced features, and to insert several passive components, such as resistors or capacitors, to properly bias the gate drivers. the insertion of filter capacitors, directly across the gate driver pins, improves the sllimm noise immunity and helps users to work in a safer condition. figure 27 shows the internal pcb detail. 3.3 package structure figure 28 and figure 29 contain images and an internal structure illustration of the sdip- 25l and sdip-38l package. figure 27. pcb structure doc id 18441 rev 4 41/72 AN3338 package 72 figure 28. images and internal view of sdip-25l package top view bottom view internal view x = 44.4 mm y 1 = 22 mm (body only) y 2 = 25.22 mm (including leads) z 1 = 5.4 mm (body only) z 2 = 11.6 mm (including leads) main dimensions sllimm sdip-25l dbc ig bt fwd pcb hvic x y z package AN3338 42/72 doc id 18441 rev 4 figure 29. images and internal view of sdip-38l package top view bottom view internal view x = 49.6 mm y 1 = 24.5 mm (body only) y 2 = 29.1 mm (including leads) z 1 = 5.4 mm (body only) z 2 = 10.91 mm (including leads) main dimensions dbc igbt fwd pcb hvgd sllimm sdip-38l x y z doc id 18441 rev 4 43/72 AN3338 package 72 3.4 package outline and dimensions figure 30. outline drawing of sdip-25l package b package AN3338 44/72 doc id 18441 rev 4 table 9. sdip-25l mechanical data dim. mm min. typ. max. a 43.90 44.40 44.90 a1 1.15 1.35 1.55 a2 1.40 1.60 1.80 a3 38.90 39.40 39.90 b 21.50 22.00 22.50 b1 11.25 11.85 12.45 b2 24.83 25.23 25.63 c 5.00 5.40 6.00 c1 6.50 7.00 7.50 c2 11.20 11.70 12.20 c3 2.90 3.00 3.10 e 2.15 2.35 2.55 e1 3.40 3.60 3.80 e2 4.50 4.70 4.90 e3 6.30 6.50 6.70 d33.30 d1 5.55 e11.20 e1 1.40 f 0.85 1.00 1.15 f1 0.35 0.50 0.65 r 1.55 1.75 1.95 t 0.45 0.55 0.65 v0 6 doc id 18441 rev 4 45/72 AN3338 package 72 figure 31. outline drawing of sdip-38l package b package AN3338 46/72 doc id 18441 rev 4 3.5 input and output pins description this paragraph defines the input and output pins of sllimm. for a more accurate description and layout suggestions, please consult the relevant sections. table 10. sdip-38l mechanical data dim. mm min. typ. max. a 49.10 49.60 50.10 a1 1.10 1.30 1.50 a2 1.40 1.60 1.80 a3 44.10 44.60 45.10 b 24.00 24.50 25.00 b1 11.25 11.85 12.45 b2 27.10 27.60 28.10 b3 28.60 29.10 29.60 c 5.00 5.40 6.00 c1 6.50 7.00 7.50 c2 10.35 10.85 11.35 c3 2.90 3.00 3.10 e 1.10 1.30 1.50 e1 3.20 3.40 3.60 e2 5.80 6.00 6.20 e3 4.60 4.80 5.00 e4 5.60 5.80 6.00 e5 6.30 6.50 6.70 e6 4.50 4.70 4.90 d 38.10 d1 5.75 e11.80 e1 2.15 f 0.85 1.00 1.15 f1 0.35 0.50 0.65 r 1.55 1.75 1.95 t 0.45 0.55 0.65 v0 6 doc id 18441 rev 4 47/72 AN3338 package 72 figure 32. pinout of sdip-25l package (bottom view) 0 $ 5 . , 1 * $ 5 ( $ table 11. input and output pins of sdip-25l package pin # name description stgips10k60a stgips14k60 stgips20k60 stgips10k60a stgips14k60 stgips20k60 1out u high side reference output for u phase 2v bootu bootstrap voltage for u phase 3lin u lin u low side logic input for u phase (active high) low side logic input for u phase (active low) 4hin u high side logic input for u phase 5v cc low voltage power supply 6out v high side reference output for v phase 7v bootv bootstrap voltage for v phase 8 gnd ground 9lin v lin v low side logic input for v phase (active high) low side logic input for v phase (active low) 10 hin v high side logic input for v phase 11 out w high side reference output for w phase 12 v bootw bootstrap voltage for w phase 13 lin w lin w low side logic input for w phase (active high) low side logic input for w phase (active low) 14 hin w high side logic input for w phase 15 t 1 sd / od ntc thermistor terminal 1 sd logic input (active low) / open drain (comp output) 16 t 2 cin ntc thermistor terminal 2 comparator input 17 n w negative dc input for w phase 18 w w phase output 19 p positive dc input 20 n v negative dc input for v phase package AN3338 48/72 doc id 18441 rev 4 pin # name description stgips10k60a stgips14k60 stgips20k60 stgips10k60a stgips14k60 stgips20k60 21 v v phase output 22 p positive dc input 23 n u negative dc input for u phase 24 u u phase output 25 p positive dc input table 11. input and output pins of sdip-25l package (continued) figure 33. pinout of sdip-38l package (bottom view) 0 $ 5 . , 1 * $ 5 ( $ table 12. input and output pins of sdip-38l package pin # stgipl14k60 stgipl20k60 name description 1out u high side reference output for u phase 2v bootu bootstrap voltage for u phase 3lin u low side logic input for u phase (active low) 4hin u high side logic input for u phase 5op -u op amp inverting input for u phase 6op outu op amp output for u phase 7op +u op amp non inverting input for u phase 8cin u comparator input for u phase 9out v high side reference output for v phase 10 v bootv bootstrap voltage for v phase 11 lin v low side logic input for v phase (active low) 12 hin v high side logic input for v phase doc id 18441 rev 4 49/72 AN3338 package 72 pin # stgipl14k60 stgipl20k60 name description 13 op -v op amp inverting input for v phase 14 op outv op amp output for v phase 15 op +v op amp non inverting input for v phase 16 cin v comparator input for v phase 17 out w high side reference output for w phase 18 v bootw bootstrap voltage for w phase 19 lin w low side logic input for w phase (active low) 20 hin w high side logic input for w phase 21 op -w op amp inverting input for w phase 22 op outw op amp output for w phase 23 op +w op amp non inverting input for w phase 24 cin w comparator input for w phase 25 v cc low voltage power supply 26 sd / od shutdown logic input (active low) / open drain (comparator output) 27 gnd ground 28 t 2 ntc thermistor terminal 2 29 t 1 ntc thermistor terminal 1 30 n w negative dc input for w phase 31 w w phase output 32 p positive dc input 33 n v negative dc input for v phase 34 v v phase output 35 p positive dc input 36 n u negative dc input for u phase 37 u u phase output 38 p positive dc input table 12. input and output pins of sdip-38l package (continued) package AN3338 50/72 doc id 18441 rev 4 high-side bias voltage pins /high-side bias voltage reference pins: v bootu -out u , v bootv -out v , v bootw -out w ? the bootstrap section is designed to realize a simple and efficient floating power supply, in order to provide the gate voltage signal to the high-side igbts. ? the sllimm family integrates the bootstrap diodes. this helps customer to save cost, board space, and number of components. ? the advantage of the ability to bootstrap the circuit scheme is that no external power supplies are required for the high-side igbts. ? each bootstrap capacitor is charged from the v cc supply during the on-state of the corresponding low side igbt. ? to prevent malfunctions caused by noise and ripple in supply voltage, a good quality (low esr, low esl) filter capacitor should be mounted close to these pins. ? the value of bootstrap capacitors is strictly related to the application conditions. please consult section 2.3.12: bootstrap circuit . gate driver bias voltage pin: v cc ? control supply pin for the built-in ics. ? to prevent malfunctions caused by noise and ripple in the supply voltage, a good quality (low esr, low esl) filter capacitor should be mounted close to this pin. gate drive supply ground pin: gnd ? ground reference pin for the built-in ics. ? to avoid noise influences, the main power circuit current should not be allowed to flow through this pin (see section 5.1: layout suggestions ). signal input pins: hin u , hin v , hin w ; lin u , lin v , lin w ; lin u , lin v , lin w ? these pins control the operation of the built-in igbts. ? the signal logic of hin u , hin v , hin w , lin u , lin v , and lin w pins is active high. the igbt associated with each of these pins is turned on when a sufficient logic (higher than a specific threshold) voltage is applied to these pins. ? the signal logic of lin u , lin v , lin w pins is active low. the igbt associated with each of these pins is turned on when a logic voltage (lower than a specific threshold voltage) is applied to these pins. ? the wiring of each input should be as short as possible to protect the sllimm against noise influences. doc id 18441 rev 4 51/72 AN3338 package 72 internal comparator non-inverting pins: cin u , cin v , cin w ? the current sensing shunt resistor, connected on each phase leg, could be used by the internal comparator (pins cin u , cin v and cin w ) to detect short-circuit current. ? the shunt resistor should be selected to meet the detection levels matched for the specific application. ? an rc filter (typically ~ 1 s) should be connected to the cin u , cin v , cin w pins to eliminate noise. ? the connection length between the shunt resistor and cin u , cin v , cin w pins should be minimized. ? if a voltage signal, higher than the specified v ref (see datasheet), is applied to this pin, the sllimm automatically shuts down and the sd / od pin is pulled down (to inform the microcontroller). shutdown / open drain pin: sd / od ? the sd / od pin works as an enable/disable pin. ? the signal logic of the sd / od pin is active low. the sllimm shuts down if a voltage lower than a specific threshold is applied to this pin, leading each half bridge in tri-state. ? the sd / od status is connected also to the internal comparator status ( section 2.3.6: short-circuit protection and smart shutdown function ). when the comparator triggers, the sd / od pin is pulled down acting as a fault pin. ? the sd / od, when pulled down by the comparator, is open drain configured. the sd / od voltage should be pulled up to the 3.3 v or 5 v logic power supply through a pull-up resistor. thermistor pins: t 1 , t 2 ? a co-packaged ntc is available for temperature monitor purposes. ? a simple voltage divider (as shown in section 2.3.10: overtemperature protection ) can be realized with an external resistor in order to realize a temperature dependent voltage signal. ? the ntc is not able to sense igbt junction temperature fast variation (due to its slow dynamic). integrated operational amplifier (only for stgipl14k60 and stgipl20k60) pins: op- u , op- v , op- w ; op outu , op outv , op outw ; op u , op v , op w ? the op amps are completely uncommitted. ? the op amps performances are optimized for advanced control technique (foc). ? thanks to the integrated op amps it is possible to realize compact and efficient board layout, minimizing the required bom list. package AN3338 52/72 doc id 18441 rev 4 positive dc-link pin: p ? these are three dc-link positive power supply pins of the inverter, which offer designers more flexibility in their approach. they are internally connected to the collectors of the high-side igbts. ? to suppress the surge voltage caused by the dc-link wiring or pcb pattern inductance, connect decoupling capacitors close to this pin and power ground (typically, high frequency, high voltage, non-inductive capacitors of about 0.1 or 0.22 f are used). negative dc-link pins: n u , n v , n w ? these are the dc-link negative power supply pins (power ground) of the inverter. ? these pins are connected to the low side igbt emitters of each phase. ? the power ground of the application should be separated from the logic ground of the system and they should be reconnected at one specific point (star connection). inverter power output pins: u, v, w ? inverter output pins for connecting to the inverter load (e.g. motor). doc id 18441 rev 4 53/72 AN3338 power losses and dissipation 72 4 power losses and dissipation the total power losses in an inverter are comprised of conduction losses, switching losses, and off-state losses and they are essentially generated by the power devices of the inverter stage, such as the igbts and the freewheeling diodes. the conduction losses (p cond ) are the on-state losses during the conduction phase. the switching losses (p sw ) are the dynamic losses encountered during the turn-on and the turn-off. the off-state losses, due to the blocking voltage and leakage current, can be neglected. finally, the total power losses are given by: equation 17 figure 34 shows a typical waveform of an inductive hard switching application such as a motor drive, where the major sources of power losses are specified. 4.1 conduction power losses the conduction losses are caused by igbt and freewheeling diode forward voltage drop at rated current. they can be calculated using a linear approximation of the forward characteristics for both igbt and diode, having a series connection of dc voltage source representing the threshold voltage, v to for igbt, (and v fo for diode) and a collector emitter on-state resistance, r ce , (and anode cathode on-state resistance, r ak ), as shown in figure 35 , for reference. sw cond tot p p p + figure 34. typical igbt power losses am09357v1 v ce i c 10% i c 10% v ce 10% v ce 10% i c e sw(on) e sw(off) v ce(sat) t c(on) t c(off) conduction power losses and dissipation AN3338 54/72 doc id 18441 rev 4 both forward characteristics are temperature dependent, and so must be considered under a specified temperature. the linear approximations can be translated for igbt in the following equation: equation 18 and, for freewheeling diode: equation 19 the conduction losses of igbt and diode can be derived as the time integral of the product of conduction current and voltage across the devices, as follows: equation 20 equation 21 where t is the fundamental period. the different utilization mode of sllimm, modulation technique, and working conditions make the power losses very difficult to estimate, it is therefore necessary to fix some starting points. figure 35. igbt and diode approximation of the output characteristics v to r ce = v ce / i c i c v ce v to r ce = v ce / i c i c v ce v fo r ak = v fm / i fm i fm v fm v fo r ak = v fm / i fm i fm v fm am09345v1 c ce to c ce i r v ) (i v ? + = ) ( ? + = ? ? ? ? ? ? ? ? ? + ? = ? = t 0 2 c ce c to t 0 c ce cond_igbt dt (t) i r (t) i v t 1 (t)dt i v t 1 p ? ? ? ? ? ? ? ? ? + ? = ? = t 0 2 f ak f fo t 0 f f cond_diode dt (t) i r (t) i v t 1 (t)dt i v t 1 p doc id 18441 rev 4 55/72 AN3338 power losses and dissipation 72 assuming that: 1. the application is a variable voltage variable frequency (vvvf) inverter based on sinusoidal pwm technique 2. the switching frequency is high and therefore the output currents are sinusoidal 3. the load is ideal inductive. under these conditions, the output inverter current is given by: equation 22 where ? is the current peak, stands for t and is the phase angle between output voltage and current. the conduction power losses can be obtained as: equation 23 equation 24 where is the duty cycle for this pwm technique and is given by: equation 25 and m a is the pwm amplitude modulation index. finally, solving equation 23 and equation 24 , we have: equation 26 equation 27 () = - cos i ? i () () ? + ? = ? ? + + ? + + ? d - cos 2 i ? r d - cos 2 i ? v p 2 2 2 2 2 2 ce to cond_igbt ()() () () ? ? + + ? + + ? ? + ? = 2 2 2 2 d - cos 1 2 i ? r d - cos 1 2 i ? v p 2 2 ak fo cond_diode 2 cos m 1 a ? + = p cond_igbt v to ? 1 2 ----- - m a cos ? 8 ----------------------- - + ?? ?? r ce ? 2 1 8 -- - m a cos ? 3 ----------------------- - + ?? ?? ? + ? = p cond_diode v fo ? 1 2 ----- - m a cos ? 8 ----------------------- - + ?? ?? r ak ? 2 1 8 -- - m a cos ? 3 ----------------------- - + ?? ?? ? + ? = power losses and dissipation AN3338 56/72 doc id 18441 rev 4 and therefore, the conduction power losses of one device (igbt and diode) are: equation 28 of course, the total conduction losses per inverter are six times this value. 4.2 switching power losses the switching loss is the power consumption during the turn-on and turn-off transients. as already shown in figure 34 , it is given by the pulse of power dissipated during the turn-on (t on ) and turn-off (t off ). experimentally, it can be calculated by the time integral of product of the collector current and collector-emitter voltage for the switching period. anyway, the dynamic performances are strictly related to many parameters such as voltage and current, temperature, so it is necessary to use the same assumptions of conduction power losses ( section 4.1: conduction power losses ) to simplify the calculations. under these conditions, the switching energy losses are given by: equation 29 equation 30 where on and off are the maximum values taken at t jmax and ? c , stands for t and is the phase angle between output voltage and current. finally, the switching power losses per device depend on the switching frequency (f sw ) and are calculated as follows: equation 31 where e igbt and e diode are the total switching energy for igbt and freewheeling diode, respectively. also in this case, the total switching losses per inverter are six times this value. figure 36 shows the real turn-on and turn-off waveforms of stgipl14k60 under the following conditions: ? v pn = 300 v, i c = 7 a, t j = 25 c with inductive load on full bridge topology, taken on the high side igbt. the red plots represent instantaneous power as a result of i c (in blue) and v ce (in green) waveforms multiplication, during the switching transitions. the areas under these plots are the switching energies computed by graphic integration thanks to the digital oscilloscope. cond_diode cond_igbt cond p p p + = () = - cos e ? ) ( e on on () = - cos e ? ) ( e of f off ? + + ? + = ? + = 2 2 - sw diode igbt sw diode igbt sw f ) e e ( d f ) e e ( 2 1 p doc id 18441 rev 4 57/72 AN3338 power losses and dissipation 72 e on and e off are the areas under the red plots. 4.3 thermal impedance overview during operation, power losses generate heat which elevates the temperature in the semiconductor junctions contained in the sllimm, limiting its performance and lifetime. to ensure safe and reliable operation, the junction temperature of power devices must be kept below the limits defined in the datasheet, therefore, the generated heat must be conducted away from the power chips and into the environment using an adequate cooling system. the most common schemes are based on one heatsink designed for free conventional air flow or, in some cases, for forced air operation. free conventional air flow systems require bigger heatsinks (about 50% more) than a forced air based heatsink, for a given thermal resistance. therefore, the choice of the cooling system becomes the starting point for the application designer and the thermal aspect of the system is one of the key factors in designing high efficiency and high reliability equipment. in this environment the package and its thermal resistance play a fundamental role. thermal resistance quantifies the capability of a given thermal path to transfer heat in the steady-state and it generically is given as the ratio between the temperature increase above the reference and the relevant power flow: equation 32 the thermal resistance specified in the datasheet is the junction-case r th(j-c) which is defined as the difference in temperature between junction and case reference divided by the power dissipation per device: figure 36. typical switching waveforms of stgipl14k60 ! - v v ce e on =142 j(*) i c t on = 264ns v hin = 5v/div i c = 2a/div v ce = 100v/div t = 80ns/div e on = (v ce i c ) dt v hin tu rn on stgipl14k60 high side tj=25 r c tu rn off stgipl14k60 high side tj=25 r c v hin i c v ce e off =100 j(*) t off = 332ns p t r th = power losses and dissipation AN3338 58/72 doc id 18441 rev 4 equation 33 the sllimm family benefits from the state of the art dbc substrate and therefore offers a very low r th(j-c) value. the backside of the dbc substrate is used as the cooling interface to the heatsink. thermal grease or another thermal interface material between the dbc and the heatsink is used to reduce the thermal resistance of the interface (r th(c-h) ) and, of course, it depends of the material and its thickness. basically, the sum of the three thermal resistance components mentioned above gives the thermal resistance between junction and ambient r th(j-a) , as shown in figure 37 . as the power loss p tot is cyclic, also the transient thermal impedance must be considered. it is defined as the ratio between the time dependent temperature increase above the reference, t(t), and the relevant heat flow: equation 34 contrary to that already seen, regarding the thermal resistance, the thermal impedance is typically represented by an rc equivalent circuit. for pulsed power loss, the thermal capacitance effect delays the rise in junction temperature and therefore the advantage of this behavior is the short-term overload capability of the sllimm. for example, figure 38 shows thermal impedance from junction to case curves of stgips14k60 (in sdip-25l package) and stgipl14k60 (in sdip-38l package). as per all the other sllimm curves, the thermal impedance reaches saturation in about 10 seconds. d c j c) - th(j p t t r ? = figure 37. equivalent thermal circuit with heatsink single igbt ! - v t j r th(h-a) t c t h t amb r th(j-c) r th(c-h) sllimm power stage dbc igbt fwd p tot ambient heatsink case junction p ) t ( t ) t ( th = doc id 18441 rev 4 59/72 AN3338 power losses and dissipation 72 more generally, in the case of the device, power is time dependent too. the device temperature can be calculated by using the convolution integral method applied to equation 34equation 34 , as follows: equation 35 an alternative method, very useful for the simulator tools, is the transient thermal impedance model, which provides a simple method to estimate the junction temperature rise under a transient condition. by using the thermo-electrical analogy, the transient thermal impedance z th (t) can be transformed into an electrical equivalent rc network. the number of rc sections increases the model details, therefore a ninth order m odel, based on the cauer network, has been used in order to improve the accuracy of the model, as shown the figure 39 . temperatures inside the electrical rc networ k represent voltages, power flows represent currents, electrical resistances and capacitances represent thermal resistances and capacitances respectively. the case temperature is represented with a dc voltage source and can be interpreted as the initial junction temperature. figure 38. thermal impedance curves (stgips14k60 and stgipl14k60) am09348v1 stgips14k60 0 1 2 3 4 1.e-05 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 1.e+02 time (sec) z th(j-c) (c/w) stgipl14k60 0 1 2 3 4 1.e-05 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 1.e+02 time (sec) z th(j-c) (c/w) ? ? = ? d ) ( p ) t ( z ) t ( t t 0 th figure 39. thermal impedance rc cauer thermal network ! - v 7 m 3 w r w w c1 c1 c2 c2 c3 c3 c4 c4 c5 c5 c6 c6 c7 c7 c8 c8 c9 c9 r1 r2 r4 r3 r5 r6 r8 r7 r9 7 f d v h = w k w power losses and dissipation AN3338 60/72 doc id 18441 rev 4 transient thermal impedance models are derived by curve fitting an equation to the measured data. values for the individual resistors and capacitors are the variables from that equation and are defined device by device in tab le 1 3 . 4.4 power losses calculation example as a result of power loss calculation and thermal aspects, fully treated in the previous sections, we are able to simulate the maximum i c(rms) current versus switching frequency curves for a vvvf inverter using a 3-phase continuous pwm modulation to synthesize sinusoidal output currents. the curves graphed in figure 40 represent the maximum current managed by sllimm in safety conditions, when the junction temperature rises to the maximum junction temperature of 150 c and case temperature is 100 c, which is a typical operating condition to guarantee the reliability of the system. these curves, functions of the motor drive typology and control scheme, are simulated under the following conditions: ? v pn = 300 v, m a = 0.8, cos = 0.6, t j = 150 c, t c = 100 c, f sine = 60 hz, max. value of r th(j-c) , typical v ce(sat) and e tot values. table 13. rc cauer thermal network elements by device element stgips10k60a stgips14k60 stgipl14k60 stgips20k60 stgipl20k60 r1 (c/w) 8.80e-02 1.61e-02 8.15e-03 1.00e-04 3.85e-03 r2 (c/w) 1.54e-02 9.42e-02 1.07e-01 5.00e-03 1.50e-02 r3 (c/w) 3.16e-01 1.20e-02 5.00e-02 7.00e-02 5.17e-03 r4 (c/w) 3.96e-03 3.50e-01 2.00e-01 1.03e-02 4.68e-02 r5 (c/w) 8.16e-01 5.86e-01 6.57e-01 6.00e-01 4.18e-01 r6 (c/w) 4.32e-01 1.58e-03 1.00e-02 1.15e-01 6.71e-02 r7 (c/w) 1.23e-02 7.50e-01 8.00e-01 1.00e-03 1.27e-01 r8 (c/w) 4.48e-01 1.60e-02 2.00e-02 1.00e-01 6.14e-01 r9 (c/w) 1.66e+00 1.10e+00 9.50e-01 1.50e+00 0.90e+00 c1 (wsec/c) 3.20e-04 9.20e-04 1.00e-03 1.80e-03 1.50e-03 c2 (wsec/c) 6.30e-04 9.07e-05 9.96e-05 3.09e-05 9.82e-05 c3 (wsec/c) 9.00e-05 1.00e-03 9.59e-05 8.94e-05 9.62e-05 c4 (wsec/c) 5.00e-04 4.14e-05 1.85e-05 9.29e-05 9.48e-05 c5 (wsec/c) 5.00e-03 1.40e-02 9.68e-03 1.20e-02 9.97e-03 c6 (wsec/c) 1.20e-02 3.57e-05 2.00e-02 7.04e-05 7.86e-05 c7 (wsec/c) 1.49e-03 3.00e-03 1.76e-03 2.93e-04 2.91e-03 c8 (wsec/c) 8.09e-04 5.75e-04 8.27e-04 9.43e-04 5.50e-02 c9 (wsec/c) 1.20e-01 1.54e-01 5.00e-01 1.00e-01 6.21e-02 doc id 18441 rev 4 61/72 AN3338 power losses and dissipation 72 figure 40. maximum i c(rms) current vs. f sw simulated curves ! - v 4 6 8 10 12 14 16 18 20 22 4 8 12 16 20 f sw (khz) maximum i c(rms) current (a) stgips10k60a stgips14k60 stgipl14k60 stgips20k60 stgipl20k60 design and mounting guidelines AN3338 62/72 doc id 18441 rev 4 5 design and mounting guidelines in this section the main layout suggestions for an optimized design and major mounting recommendations, to appropriately handle and assemble the sllimm family, are introduced. 5.1 layout suggestions optimization of pcb layout for high voltage, high current and high switching frequency applications is a critical point. pcb layout is a complex matter as it includes several aspects, such as length and width of track and circuit areas, but also the proper routing of the traces and the optimized reciprocal arrangement of the various system elements in the pcb area. a good layout can help the application to properly function and achieve expected performance. on the other hand, pcb without a careful layout can generate emi issues (both induced and perceived by the application), can provide overvoltage spikes due to parasitic inductances along the pcb traces, and can produce higher power loss and even malfunction in the control and sensing stages. the compactness of the sllimm solution, which offers optimized gate driving network and reduced parasitic elements, allows designers to focus only on some specific issues, such as the ground issue or noise filter. anyhow, in order to avoid all the aforementioned conditions, the following general guidelines and suggestions must be followed in pcb layout for 3- phase applications. 5.1.1 general suggestions ? pcb traces should be designed to be as short as possible and the area of the circuit (power or signal) should be minimized to avoid the sensitivity of such structures to surrounding noise. ? ensure a good distance between switching lines with high voltage transitions and the signal line sensitive to electrical noise. specifically, the tracks of each out phase, bringing significant currents and high voltages, should be separated from the logic lines and analog sensing circuit of op amps and comparators. ? place the r sense resistors as close as possible to the low side pins of the sllimm (n u , n v and n w ). parasitic inductance can be minimized by connecting the ground line (also called driver ground) of the sllimm directly to the cold terminal of sense resistors. use of a low inductance type resistor, such as an smd resistor instead of long-lead type resistors, can help to further decrease the parasitic inductance. ? avoid any ground loop. only a single path must connect two different ground nodes. ? place each rc filter as close as possible to the sllimm pins in order to increase their efficiency. ? in order to prevent surge destruction, the wiring between the decoupling capacitor and the p pin and power ground should be as short as possible. the use of a high doc id 18441 rev 4 63/72 AN3338 design and mounting guidelines 72 frequency, high voltage non-inductive capacitor about 0.1 or 0.22 f between the p and n pins is recommended. ? fixed voltage tracks, such as gnd or hv lines, can be used to shield the logic and analog lines from the electrical noise produced by the switching lines (e.g. out u , out v and out w ). ? generally it is recommended to connect each half bridge ground in a star configuration and the three r sense very close to each other and to the power ground. in figure 41 and figure 42 the general suggestions for all sllimm products are summarized. figure 41. general suggestions 1 v in(ul) v in(uh) to mcu p u p p v w out u v bootu lin u hin u v cc v bootv out v lin v hin v out w v bootw lin w hin w sd/od cin n v shutdown/fault use of low inductance type res is tor, such as smd resistor instead of long-lead type res is tor, can help to further decrease the parasitic inductance wiring between n u ,n v ,n w and shunt resistor should be as short as possible c onnect all signal ground to geth e r a nd th e n c onnec t th e signal ground and power ground at only one point bootstrap capacitor should be located as close as possible to the sllimm pins isolation distances between high voltage block (bootstrap) and low voltage block mus t be kept s ignal ground and power ground must be connected at only one point (star connections) avoiding long connections. please ensure a safety distances between ground tracks and noisy tracks (high voltage or high frequency s ignals tracks) cin connections must be as short as possible connect cin filter capacitor to signal ground. t his connection should be as short as possible v in(vl) v in(vh) to mcu v in(wl) v in(wh) to mcu +3.3v +15v gnd from power source to moto r gnd n u layer 1 layer 2 + - power gnd (n) shunt resis tor n w bus capacitor decoupling capacitor am09351v1 design and mounting guidelines AN3338 64/72 doc id 18441 rev 4 special attention must be paid to some wrong layouts. in figure 43 and figure 44 some common pcb mistakes are shown. figure 42. general suggestions 2 power gnd (n) shunt resis tors + - p u p p w out u v bootu lin u hin u v cc v bootv out v lin v hin v out w v bootw lin w hin w sd/od n v op- u op- v op outv op- w t 2 t 1 op outw gnd op outu v in(ul) v in(uh) to mcu shutdown/fault v in(vl) v in(vh) to mcu v in(wl) v in(wh) to mcu +3.3v +15v gnd p hase current v p hase current w p hase current u temp feedback n u op+ u cin u v op+ v cin v n w cin w op+ w use of low inductance type resistor, such as smd one, can help to further decrease the parasitic inductance bootstrap capacitor s hould be located as close as pos s ible to th e sllimm pins isolation distances between high voltage block (bootstrap) and low voltage block mus t be kept reduce all distances between shunt resistors and sllimm power gnd s ignal ground and power ground must be connected at only one point (star connections), avoiding long connections. please ensure a safety distances between ground tracks and noisy tracks (high voltage or high frequency signals tracks) to moto r c onne ct a ll th e s igna l ground together and a fte r th is, c onnec t th e m to th e power ground a t only one point ntc will provide a te mpe ra ture feedback to th e mcu place an rc filter directly across sd pin place an r c filter directly across the cin (for each phase) pin to avoid false s hort- c ircuit tr igge r p la ce th e s md c ompone nts a s close as possible the op amp pins. keep a safety distance between noisy tr a cks a nd op a mp c in tr a cks layer 1 layer 2 bus capacitor decoupling capacitor am09352v1 doc id 18441 rev 4 65/72 AN3338 design and mounting guidelines 72 figure 43. example 1 of a possible wrong layout wrong! s tub connections and vias produce reflections, especially on critical signal tracks. prefer star connections and reduce number of vias v in(ul) v in(uh) to mcu p u p p v w out u v bootu lin u hin u v cc v bootv out v lin v hin v out w v bootw lin w hin w sd/od gnd + - n u n w shunt resis tor power gnd (n) shutdown/fault wrong! c in filter ground is not the same as per sllimm ground. t his may cause noise wrong! cin filter is close to high voltage s witching track (w pin). noise will influence comparator performances wrong! long distance between cin filter and sllimm cin pin. it is important to minimize this dis tance in order to reduce the noise impact v in(vl) v in(vh) to mcu v in(wl) v in(wh) to mcu +3.3v +15v gnd from power source to moto r cin n v cin f ilter layer 1 layer 2 bus capacitor decoupling capacitor wrong! decoupling capacitor is too far from sllimm. c onnect it as close as pos s ible to th e p pin wrong! r ight-angled track turns produce a field concentration at the inner edge. prefer 45 angled tracks am09353v1 design and mounting guidelines AN3338 66/72 doc id 18441 rev 4 5.2 mounting instructions the purpose of the mounting instructions is to define some basic assembly rules in order to limit thermal and mechanical stresses or assure the best thermal conduction and electrical isolation of both sdip-25l and sdip-38l packages when mounting on a heatsink. for further details please refer to the tn0107 technical note. 5.2.1 heatsink mounting the following precautions should be observed to maximize the effect of the heatsink and minimize stresses on the device. smooth the surface by removing burrs and protrusions; it is essential to ensure an optimal contact between the sllimm and the heatsink. apply a uniform layer of silicon grease, from 100 m up to 200 m of thickness, between the device and the heatsink to reduce the contact thermal resistance, as shown in figure 45 . be sure to apply the coating thinly and evenly, paying attention to not having any voids remaining on the contact surface between the sllimm and the heatsink. we recommend using high quality grease with stable performance within the operating temperature range of the sllimm. figure 44. example 2 of a possible wrong layout ! - v sllimm grou nd bulk capacitor ground path sense resistor cold terminal wrong! ve ry large ground loop. does not used the suggested star connection. long ground path could be affected by noise (due to high voltage switching tracks) and could affect driver (or application) performance wrong! connection between the sllimm and ground is not minimized wrong! the cold terminal of the sense resistor is not chosen as star centre sllimm doc id 18441 rev 4 67/72 AN3338 design and mounting guidelines 72 5.2.2 mounting torque while mounting the sllimm to a heatsink make sure not to apply excessive force during the assembly. ta ble 14 provides the specified fastening torque. inappropriate mounting can damage the device and over tightening the screws may cause dbc substrate or molding compound cracks. avoid mechanical stress due to tightening on one side only. it is recommended to temporarily fasten both screws, then fasten them permanently to the specified torque value using a torque wrench. figure 47 shows the screw fastening order. figure 45. recommended silicon grease thickness and positioning ! - v heatsink 6 l o l f r q j u h d v h 100~200 m thickness sllimm table 14. mounting torque and heatsink flatness parameter limits units min. typ. max. mounting torque (m3 screw) 0.4 0.7 1.0 nm heatsink flatness -50 150 m sdip-25l package weight 13 g sdip-38l package weight 17 g design and mounting guidelines AN3338 68/72 doc id 18441 rev 4 5.2.3 general handling precaution and storage notices the incidence of thermal and/or mechanical stress to the semiconductor devices due to improper handling may result in significant deterioration of their electrical characteristics and/or reliability. figure 46. measurement point of cu heatsink flatness ! - v 4 o p v i e w # u h e a t s i n k s u r f a c e figure 47. recommended fastening order of mounting screws ! - v 4 e m p o r a r y f a s t e n i n g 0 e r m a n e n t f a s t e n i n g doc id 18441 rev 4 69/72 AN3338 design and mounting guidelines 72 the sllimm is an esd sensitive device, it may be damaged in the case of esd shocks. all equipment used to handle power modules must comply with esd standards including transportation, storage, and assembly. transportation be careful when handling the sllimm and packaging material. ensure that the module is not subjected to mechanical vibration or s hock during transport. do not toss or drop to ensure the sllimm is correctly functioning before boarding. wet conditions are dangerous and moisture can also adversely affect the packaging. hold the package avoiding touching the leads during mounting. put package boxes upside down, leaning them or giving them uneven stress may cause the terminals to be deformed or the resin to be damaged. throwing or dropping the packaging boxes may cause the modules to be damaged. wetting the packaging boxes may cause the breakdown of modules when operating. pay particular care when transporting in wet conditions. storage ? do not force or load the external pressure to the modules while they are in storage ? humidity should be kept within the range of 40% to 75%, the temperature should not go over 35 c or below 5 c ? lead solder ability is degraded by lead oxidation or corrosion. so using storage areas where there is minimal temperature fluctuation is highly recommended ? the presence of harmful gases or dusty conditions is not acceptable for storage. ? use antistatic containers electrical shock and thermal injury ? do not touch either module or heatsink when sllimm is operating to avoid sustaining an electrical shock and/or a burn injury. references AN3338 70/72 doc id 18441 rev 4 6 references 1. stgips10k60a datasheet 2. stgips14k60 datasheet 3. stgipl14k60 datasheet 4. stgips20k60 datasheet 5. stgipl20k60 datasheet 6. an2738 application note 7. um0969 user manual 8. um0900 user manual 9. um1036 user manual 10. minimum-loss strategy for three-phase pwm rectifier, ieee, june 1999 11. tn0107 technical note. note: sllimm? and powermesh? are trademarks of stmicroelectronics. doc id 18441 rev 4 71/72 AN3338 revision history 72 7 revision history table 15. document revision history date revision changes 21-mar-2011 1 initial release. 12-jul-2011 2 modified: r thjc table 1 on page 9 , figure 32 on page 47 and heatsink flatness max. value table 14 on page 67 . 17-sep-2012 3 updated: figure 4 on page 10 , figure 18 on page 30 , figure 41 on page 63 , figure 42 on page 64 and figure 43 on page 65 . 17-mar-2015 4 updated product features in section 1.1 added footnote to table 1 updated figures: figure 4 , figure 14 , figure 16 , figure 22 , figure 23 , figure 30 , figure 31 removed footnote from table 5 updated table 9 , table 10 in section 3.5 , updated positive dc-link pin details updated equations 26 and 27 updated table 13 removed section 5.2.4 packaging specifications AN3338 72/72 doc id 18441 rev 4 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved |
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